Generally, in a DRAM (dynamic random access memory) the contents of all the memory cells in a specified row are read by a sense amplifier, and the contents are rewritten in the same memory cells, thus completing a basic operating cycle. If the contents of all of the bits in a specified column are read and output externally, the operation is a read cycle. If the contents of the bits in a specified column are changed before rewriting, the operation is a write cycle. If both processes are executed, the operation is a read (modify) write cycle.
As described above, in a DRAM, first, a row is read, and a column is selected thereafter, wherein a row address and a column address are obtained from memory using a time division or a so-called multiplex method.
In this conventional semiconductor storage device prior art, the multiplexed row address signal and column address signal are obtained from memory in accordance with a row address strobe signal (hereinafter, RAS) and a column address strobe signal (hereinafter CAS). Both of these strobe signals are negative logic signals and the falling edge is defined as an address signal fetch timing. Accordingly, in the RASor CAS, the signal is changed from inactive to active at the falling edge and is changed from active to inactive at the rising edge.
Namely, for example, in a DRAM comprising N channel MOS transistors, a circuit is precharged at the rising edge of the RAS, at the falling of the RAS a circuit on the row side is operated dynamically and the row address signal is fetched. Then, after the content of the signal is decoded and one of word lines is selected and activated, a circuit on the column side is operated dynamically at the falling of the CAS and the column address signal is fetched. Further, the content of the signal is decoded, one bit line is selected, and one memory cell connected to the above one word line and one bit line is accessed.
In such a DRAM, however, the time required to access one memory cell starts from the falling of the RAS and until the time of data outputting. In this case, since the operation of the column side, in response to the fall of the CAS, does not start immediately after the operation of the row side, sufficiently high speed access is not achieved.
As another prior art example, a DRAM using a so-called fast column method is known Wherein each circuit is precharged at the rising of the RAS, at an appropriate time after the falling of the RAS an internal timing signal is generated, and in accordance with this signal, the column address is automatically fetched. In this DRAM, a memory cell can be accessed without waiting for the falling of the CAS, and a high speed operation can be planned.
In such a conventional DRAM using the fast column method, however, although an effect which is substantially equivalent to advancing the falling time of the CAS is obtained, since access start timing for the row side input address assigned to memory depends on the falling time of the RAS, there is a problem in that it is necessary to plan for higher access speed.